1. Field of the Invention
The present invention relates to estimating large-scale integrated circuit (LSI) power consumption.
2. Description of the Related Art
In LSI circuits, electric power is consumed when an output signal from a device changes. When estimating the power consumption of an LSI at the design stage, how frequently the output signal from each device changes is estimated, and power consumption is estimated based on this value.
Among various power consumption values estimated at the design stage, the maximum power consumption is an important value. If the maximum power consumption is obtained, whether power supply is sufficiently assured or whether a temperature increase, even at a maximum, falls within a guaranteed operation temperature range can be verified by using this value.
When estimating the maximum power consumption at the design stage, the maximum operation ratio of operation ratios indicative of percentages of signal transition is first obtained, and the maximum operating power is estimated from this value. As techniques of estimating the maximum operation ratio, the following techniques have been proposed (see, for example, “Analysis of Maximum Switching Activities in Sequential Circuits for Power Supply Integrity Validation”, ACM/IEEE International Workshop on Logic and Synthesis 2006).
FIG. 14 is a schematic of the first technique of estimating the maximum operation ratio. As shown in FIG. 14, according to the first technique, (1) values of flip-flop circuits (hereinafter, “FFs”) in an LSI 1400 are set. (2) Then, simulation of a combinational circuit 1401 is executed by using the set values. (3) Subsequently, the number of times (signal transition number) that a signal from the combinational circuit 1401 changes is counted. Thereafter, (1) to (3) are repeatedly executed by changing the set values of the FFs.
Another technique involves using the first technique to some extent, storing the maximum operation ratio among the obtained ratios as a maximum operation ratio candidate, and then using the second technique to obtain an input pattern that provides an operation ratio greater than the maximum operation ratio candidate.
FIG. 15 is a schematic of the second technique of estimating the maximum operation ratio. As shown in FIG. 15, according to the second technique, (1) several simultaneous transition candidate points (indicated by marks x in FIG. 15), where the operation ratio increases when simultaneous transition occurs, are selected in the LSI 1400. (2) Then, based on a back calculation, it is confirmed whether an input value of the FF that induces simultaneous transition of the simultaneous transition candidate points is present.
(3) If an input value of the FF that induces simultaneous transition is present, a signal transition number is counted with respect to a pattern of the input value of the FF to calculate the operation ratio. (4) If the operation ratio calculated at (3) is higher than the maximum operation ratio candidate obtained by the first technique, the maximum operation ratio candidate is replaced by the currently selected simultaneous transition candidate point.
Thereafter, various simultaneous transition candidate points are selected, and (1) to (4) are repeatedly executed. Based on this operation, an FF input value pattern that provides a higher operation ratio is obtained. After sufficiently repeating this loop, the obtained maximum operation ratio candidate is regarded as the maximum operation ratio.
A third technique of adding a circuit that represents an input constraint before the LSI also exists (see, for example, “Symbolic Model Checking using SAT procedures instead of BDDs”, DAC1999, pp. 317-320 2; and “Improved SAT-based Bounded Reachability Analysis”, International Conference on VLSI Design 2002, pp. 729-734). According to this third technique, a circuit that represents an input constraint is generated and coupled before the LSI whose operation ratio is to be obtained.
FIG. 16 is a schematic of the first technique to which the third technique is applied, and FIG. 17 is a schematic of the second technique to which the third technique is applied. As shown in FIG. 16, (1) values of antecedent FFs, which are provided preceding a circuit representing input constraints 1601, are first set. (2) Then, simulation of the combinational circuit 1401 is executed by using the set values. At this time, the values of the FFs provided preceding the combinational circuit 1401 are set based on an output from the circuit representing input constraints 1601, and operation of the combinational circuit 1401 is simulated by using the set values. (3) Subsequently, the number of times (signal transition number) that a signal from the combinational circuit 1401 changes is counted.
Thereafter, the set values of the antecedent FFs are changed to repeatedly execute (1) to (3). According to the first technique having the third technique applied thereto, the values of the antecedent FFs are changed to count the signal transition in the combinational circuit 1401.
As shown in FIG. 17, (1) several simultaneous transition candidate points (indicated by marks x in FIG. 15) at which the operation ratio is increased when simultaneous transition occurs are first selected in the LSI. (2) Then, the presence of an input value of the antecedent FFs that induces simultaneous transition is confirmed by a back calculation.
(3) If the input value of the antecedent FFs that induces simultaneous transition is present, a signal transition number is counted with respect to a pattern of this input value of the FF to calculate an operation ratio. (4) If the operation ratio calculated at (3) is higher than the maximum operation ratio candidate obtained by the first technique, the maximum operation ratio candidate is replaced by the currently selected simultaneous transition candidate point.
According to the second technique to which the third technique is applied, whether a pattern of the values of the antecedent FFs that induces transition of a target circuit in the combinational circuit 1401 is present is checked.
However, according to the first technique, if the number of changes in signals can be counted with respect to all patterns of values of the FFs, a maximum value in operation ratios obtained from this counting can be acquired as the maximum operation ratio. In reality, 2n patterns of values of n FFs are present. Therefore, an enormous number of combinations are present, and hence covering all the combinations is difficult. That is, trying covering all the combinations results in a problem of increased design burden and a prolonged design period.
According to the second technique, a possibility of obtaining an operation ratio with respect to a pattern that is not actually present is increased. Specifically, when n FFs are present in the LSI, 2n patterns of values of these FFs are present, but all the patterns are not patterns that can be actually achieved.
2n becomes an enormous number if a value of n is large; however, for the majority of designs, only a very small part of patterns can be actually realized. Therefore, when the maximum operation ratio of the circuit is simply obtained, the possibility of acquiring an operation ratio with respect to a pattern that cannot be actually realized is increased. Accordingly, the maximum power consumption is estimated to be higher than the actual maximum power consumption, resulting in a factor of an operation failure.
FIG. 18 is a circuit diagram of an example of an input that is impossible in reality. As shown in FIG. 18, since an FF 1 and an input are inverted by an inverter INV, the FF 1 and an FF 2 do not take the same value. However, when a pattern that provides a maximum operation ratio is obtained, a pattern that the FF 1 and the FF 2 take the same value is attempted.
Therefore, when an operation ratio is the maximum in this pattern, this operation ratio is determined as the maximum operation ratio. As a result, an operation ratio higher than a true maximum operation ratio is rendered as the maximum operation ratio.
When applying the third technique, a designer must know what kind of constraints a value of the FF has in advance, and obtaining this input constraint is difficult, resulting in a problem of increased design burden and prolonged design period.